Most modern processors employ a write-back policy in their last level caches (LLCs). Consequently, writes to the dynamic random access memory (DRAM) main memory are the result of the eviction of dirty cache-lines from the LLC so they are not on the critical path for program execution. The writes are typically buffered in a write queue and are serviced when there are no reads to service or when the write queue is nearly full.
Resistive memory is one of the emerging memory technologies that may replace DRAM as the main memory in computers. Resistive memory in general refers to any technology that uses varying cell resistance to store information. One type of resistive memory is metal-oxide resistive random access memory (ReRAM).
A ReRAM cell has a metal-oxide layer sandwiched between two metal electrodes. A low resistance state (LRS or ON-state) and a high resistance state (HRS or OFF-state) are used to represent the logical “1” and ‘0” respectively or vice versa. In order to switch a ReRAM cell, an external voltage with certain polarity, magnitude, and duration is applied to the metal oxide.
Use of the same reference numbers in different figures indicates similar or identical elements.